Monday, November 4, 2013

I²C Level Shifting

A common problem with I²C is level shifting. For example the Raspberry Pi has a 3.3 V I²C interface. Connecting a 5 V I²C interface will break the Raspberry Pi. There are many possibilities, including explicit level shifting ICs. In this post I will describe a very elegant way that works quite nice and only uses two N-channel MOSFET transistors. Those should be part of every electronics toolbox. I use 2N7002 transistors, but many others should do the job, too. The source of this is an application note of NXP.

Easy I²C level shifting

The connection is the same for SDA and SCL line as depicted above. All SDA and SCL pins of 3.3 V devices should be connected to the source of the respective MOSFET while the pins of 5 V devices are connected to the drain. The gates should be connected to 3.3 V. The resistors are the I²C pull-up resistors that should be used anyway. You might want to experiment with other values to get more speed or better reliability. For me those values work quite good and enable a reliable connection of I²C devices at different voltages.

Theoretical Background

I²C is based on open collector outputs. Pull-up resistors to the positive supply make the default state high. Each IC connected to the bus can pull down the line to low. When no device accesses the I²C bus, the voltage is pulled up to the respective high voltage. This is 3.3 V on the left side and 5 V on the right side. Therefore, gate and source are on the same voltage level. No current can flow between drain and source, because the MOSFET channel is not conducting. Therefore, no damage will happen.

This changes when a 3.3 V device pulls down the line. The voltage between gate and source (Vgs) rises to 3.3 V. Now current flows from drain to source until the drain is pulled down, too. Both sides are now at low level as intended by the 3.3 V device. When a 5 V device wants to pull down the line, the process is slightly different. Since a MOSFET contains an implicit body diode, current starts flowing as soon as the source voltage is higher than the drain voltage. Vgs rises and the voltage is further pulled down until both sides are at low level.

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