Thursday, April 4, 2013

PCM/PWM Clock Calculator

I was tired of calculating the same thing over and over again. Therefore, I build this little tool for calculating the Raspberry Pi PCM/PWM clock settings according to BCM2835 Audio & PWM clocks.
The tool is provided without warranty of any kind. Please check the settings manually before applying them to your hardware.

Hint: In most cases you want to set the external divider to 1, but it can be handy if you want for example adjust a derived clock, e.g. the I2S frame sync. You can get appropriate divider settings (i.e. all integer dividers of the divisor) by hovering the mouse over the (combined) divisor field.

Questions or suggestion are gladly welcome!

By the way: Can anyone explain why someone would prefer MASH-2 or MASH-3 over MASH-1? They have a higher variance, but I don't see any advantage.
Edit: I found a note in the datasheet, that this is because of noise-shaping. This means you increase the overall noise that is introduced by the jitter, but push it into higher frequencies. This has the advantage of reducing the perceived noise when using it for audio applications.

Oscillator PLLD


  1. Thanks for putting this together. I found it while searching for info on how to configure PWM. It would be really great if you could change the source frequency, e.g., to use PLLA instead of PLLD. Incidentally, do you know where the PLL frequencies are documented? I cannot find anything authoritative about this online. What are you using PWM for, by the way? Anything interesting?

    1. I found somewhere that only PLLD is working, so I did not test the others. If you can name the frequency of another clock source, I would be glad to add this.

      The frequencies are measured with an oscilloscope, because I didn't found frequency informations, too. Maybe I will test the other clock sources later this week.

      My project does not use the PWM, but the PCM clock:

      In this project there is also a code snippet that calculates the clock frequency dynamically:
      (sampling_rate*half_frame*2 is the target frequency)

    2. I think I read the same source about PLLD, but my experiments suggest that the kernel is using PLLA (see

      There seems to be a lot of conflicting information out there. For instance, someone quotes PLLA at 650MHz, PLLB at 400MHz, and PLLD at 200MHz (derived from Gert's paper which you link to), but this doesn't match your scope measurements, so I am skeptical.

      If you were to test the other clock sources with a scope that would be fantastic information, I think a lot of people would like to know this.

    3. I predict PLLA is 393.216MHz, a number I have not seen written anywhere on the net. To correct my earlier message, the quote was that *PLLC* is 200MHz, and PLLD is 500MHz, as you found.

    4. I tried to measure the other frequencies, but there is nothing at the output when using another setting than OSC or PLLD. Maybe you can provide me a running example where you used PLLA etc.?

  2. I have only seen PLLA work when playing audio in Linux. This clock seems to be initially disabled on a bare system, and I have not figured out how to enable it. I have switched to using PLLD now, like everyone else :)

    1. This is very sad! Is it too naive to assume, that activating the other PLLs would require only setting a bit in a hidden register? In that case I wonder why this is not published.


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